Scalable 3.2 Tb/s silicon photonic transceiver architecture for AI interconnects (IMAGE)

Chinese Society for Optical Engineering

Scalable 3.2 Tb/s silicon photonic transceiver architecture for AI interconnects

Caption

Schematic of the proposed scalable 3.2 Tb/s O-band silicon photonic transceiver architecture for high-speed AI interconnects. The architecture integrates hybrid wavelength-port multiplexing, lattice-filter-based multiplexers, dual-microring-based demultiplexers, and adaptive wavelength locking to enable high-bandwidth and robust optical I/O.

Credit

Zhejiang University/Jianyi Yang, Zhejiang University/Bin Zhang

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CC BY

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